1. Field of the Invention
The present invention relates to semiconductor devices, and particularly, to a semiconductor device having an output impedance controller that controls the impedance of an output buffer with the use of an external resistor.
2. Description of Related Art
Improving MPU performance is requiring memories of faster data transfer rates. For example, external cache memories are required to operate at several hundred megahertz.
To realize such high-frequency data transfer from a memory to an MPU, the impedance of an output buffer of the memory needs to be matched with the impedance of a board data bus in consideration of data bus conditions such as signal reflection. The higher the operating frequency, the more the accuracy of impedance matching is required. To achieve this, a technique of correcting impedance errors caused by various factors is used.
In this technique, drive ability is adjusted to the predetermined value to change the size of transistors, i.e., the impedance of an output buffer of a memory if the characteristics of the transistors deviate from required ones due to manufacturing variations or varying operation conditions including operation temperatures and voltages. This technique is called a programmable impedance control function.
FIG. 1 shows a circuit according to a prior art for achieving the programmable impedance control (The source "Digest of Tech papers (IEEE) Feb. 8, 1996: ISSCC96 Page 148"). This circuit includes an output buffer 111 and an output impedance controller, which consists of elements 112 to 120 to control the output impedance of the output buffer 111. An external resistor RQ is selected as an impedance source according to which the impedance of the output buffer 111 is adjusted. The resistor RQ is connected to a ZQ-terminal. The output impedance controller controls the number of active transistors in the output buffer 111, to match the output impedance of the output buffer 111 with the impedance of the resistor RQ.
In FIG. 1, the output impedance controller includes an evaluation unit 112, a comparator 113, an up/down (U/D) counter 114, registers 115 to 117, a selector 118, a data update controller 119, and a clock generator 120.
The evaluation unit 112 has a reference current source consisting of an NMOS transistor 112a and resistors R0 and R1, and a dummy buffer consisting of transistors 1X, 2X, 4X, and 8X. The number of transistors in the dummy buffer is equal to or a multiple of the number of transistors in the output buffer 111. The reference current source generates a voltage VZQ for the ZQ-terminal and a voltage VEVAL for the dummy buffer. The voltages VZQ and VEVAL are transferred to the comparator 113. The output of the comparator 113 controls the counter 114, which turns on and off the NMOS transistors 1X to 8X of the dummy buffer to equalize the voltages VZQ and VEVAL.
In this way, the impedance of the dummy buffer is matched with that of the resistor RQ.
Data used to adjust the impedance of the dummy buffer in accordance with the resistor RQ is transferred to the output buffer 111 through the data update controller 119. Based on the data, drive transistors 1Y to 8Y and 1Z to 8Z of the output buffer 111 are selectively turned on and off to equalize the impedance of the output buffer 111 with the impedance determined by the resistor RQ.
In FIG. 1, the pull-up and pull-down sides of the output buffer 111 consist each of NMOS transistors, and therefore, manufacturing variations and operating variations on these transistors are equal. Accordingly, the dummy buffer may have a single system of NMOS transistors to control the ON/OFF states of the transistors of the output buffer 111.
If the pull-up side of the output buffer 111 is made of PMOS transistors, the dummy buffer must additionally have a system of PMOS transistors to adjust the impedance of the output buffer 111 because PMOS transistors involve different manufacturing variations from NMOS transistors.
FIG. 2 shows an output impedance controller according to a related art, for adjusting the impedance of two systems in a programmable impedance output buffer.
The output impedance controller has a reference current source 211 that includes a reference voltage generator 221. The reference voltage generator 221 uses a voltage VDDQ that is between a high voltage VDD and a low voltage VSS to apply a fixed voltage to a ZQ-terminal. The reference voltage generator 221 has voltage dividing resistors Ra and Rb and an activation NMOS transistor N20 and generates a reference voltage VDDQ/2. The reference voltage VDDQ/2 is applied to a noninverted input terminal of an operational amplifier OP1. The output of the operational amplifier OP1 controls an NMOS transistor N21 whose source is fed back to an inverted input terminal of the operational amplifier OP1. As a result, the ZQ-terminal receives the reference voltage VZQ=VDDQ/2.
The reference voltage VZQ is applied to the ZQ-terminal so that a current IZQ flows through an external resistor RQ connected to the ZQ-terminal. The current IZQ is a reference current representing the resistance of the resistor RQ. PMOS transistors P21 and P23 form a current mirror circuit that forms a current feed source 222 to feed a current from the power source VDD to a pull-down dummy buffer Ndm according to the reference current IZQ.
A current mirror circuit consisting of the PMOS transistors P21 and P22 and a current mirror circuit consisting of NMOS transistors N22 and N23 connected to the output of the current mirror circuit of P21 and P22 form a current pull-in source 223 that pulls a current from a pull-up dummy buffer Pdm into the power source VSS.
The output impedance controller also has a pull-down controller 213. The pulldown controller 213 has an operational amplifier OP2 to receive a voltage from a connection node REFIU and the voltage VZQ from the ZQ-terminal, and a U/D counter 224 for carrying out up/down counting in response to the output of the operational amplifier OP2. The output impedance controller also has a pull-up controller 215. The pull-up controller 215 has an operational amplifier OP3 to receive a voltage from a connection node REFID and the voltage VZQ from the ZQ-terminal, and a U/D counter 225 for carrying out up/down counting in response to the output of the operational amplifier OP3.
The pull-down dummy buffer Ndm has N pieces of NMOS transistors (N31 to N33 in FIG. 2). The drains of the transistors N31 to N33 are commonly connected to the connection node REFIU. The sources of the transistors N31 to N33 are commonly connected to the power source VSS, and the gate widths of these transistors are set as, for example, 1:2:4.
The counter 224 provides N pieces of output bits D0 to Dn-1 that are supplied to the gates of the transistors N31 to N33, respectively. The pull-down controller 213 determines the ON/OFF states of the transistors N31 to N33 so that a voltage at the connection node REFIU may agree with the voltage VZQ, thereby determining the impedance of the dummy buffer Ndm.
The pull-up dummy buffer Pdm has M pieces of PMOS transistors (P31 to P33 in FIG. 2). The drains of the transistors P31 to P33 are commonly connected to the connection node REFID. The sources of the transistors P31 to P33 are commonly connected to the power source VDDQ, and the gate widths of these transistors are set as, for example, 1:2:4.
The counter 225 provides M pieces of output bits U0 to Um-1, which are supplied to the gates of the transistors P31 to P33, respectively. The pull-up controller 215 determines the ON/OFF states of the transistors P31 to P33 so that a voltage at the connection node REFID may agree with the voltage VZQ, thereby determining the impedance of the dummy buffer Pdm.
In this way, the impedance of the dummy buffers Ndm and Pdm is determined according to the reference current IZQ that is based on the external resistor RQ. The output bits DO to Dn-1 and UO to Um-1 of the pull-down and pull-up controllers 213 and 215 determine the impedance of the dummy buffers Ndm and Pdm, and at the same time, are transferred to an output buffer (not shown in FIG. 2), to set the impedance of the output buffer.
Generally, the impedance of an output buffer or a dummy buffer is not always linear relative to the output level of the buffer. Accordingly, the impedance of an output buffer is defined as a value when the output level of the output buffer is 1/2 (intermediate output level) of a source voltage VDDQ for driving the output buffer. In FIG. 1, the constant current source is simply formed with the resistors RO and RI, and the impedance of the output impedance controller is set based on the resistance. of the external resistor RQ. If the range of the resistor RQ is narrow (for example, about 50 .OMEGA.), there will be no problem because the level of the ZQ-terminal is about VDDQ/2 irrespective of the resistance of the resistor RQ that is connected to the ZQ-terminal. If the range of the resistor RQ is wide (for example, 50 .OMEGA. to 70 .OMEGA.), there will be a problem because the level of the ZQ-terminal greatly varies depending on the resistance of the resistor RQ. In this case, the impedance of the output impedance controller involves an error corresponding to an impedance linear portion.
On the other hand, the output impedance controller of FIG. 2 controls the impedance thereof by equalizing the level VZQ at the ZQ-terminal as well as the drain levels of the dummy buffers Ndm and Pdm at the connection nodes REFIU and REFID with VDDQ/2. Even if the range of the external resistor RQ is wide, the resistor RQ and the impedance of each dummy buffer are compared with each other as defined, to secure the correctness of impedance provided by the output impedance controller.
The output impedance controller of FIG. 2, however, has the following problems:
(1) As the integration of LsIs improves, source voltage for the LSIs decreases. Even so, the threshold voltage Vth of each transistor in the LSIs is hardly scaled accordingly.
There is no decrease in a sub-threshold leak in response to a decrease in gate voltage because no scaling is made on the S factor (dIg/dVg) of a transistor. And a leak current becomes relatively larger as the threshold voltage Vth of the transistor decreases. Therefore, the sub-threshold leak is unignorably large with respect to a standby current.
On the other hand, the source voltage decrease and the scaled-down elements and design rules reduce load charging/discharging energy and load capacitance, to reduce a gate delay. In a circuit having serially connected transistors, however, the source voltage decrease greatly deteriorates a power source margin if no scaling is made on the threshold voltage Vth of each transistor in response to the source voltage decrease. This is because the threshold voltage Vth including a threshold voltage drop directly influences circuit operation.
This problem will be explained in more detail in connection with the prior art of FIG. 2. To equalize a current supplied to the dummy buffers Ndm and Pdm with the current IZQ flowing to the resistor RQ, the prior art employs the current mirror involving the PMOS transistors P21 to P23 and the NMOS transistors N22 and N23. The gate and drain of each of the transistors P21 and N22 are connected together to provide a standard current mirror, which causes a threshold voltage drop.
The level of the ZQ-terminal is controlled to VDDQ/2 by feeding the level of the ZQ-terminal back to the gate of the transistor N21, which clamps the level. As a result, a threshold voltage drop also occurs at the transistor N21. These threshold voltage drops deteriorate an effective transistor operation voltage.
To correctly mirror a current in the current mirror, the drain current dependence of the transistors whose gates are commonly connected must be suppressed. Namely, it is preferable to increase a drain voltage so that the transistors may operate in a saturation region. Accordingly, the deteriorated voltage margin harms the performance of the current mirror.
According to the prior art of FIG. 2, a current path of the external resistor RQ involves two threshold voltage drops caused by the transistors P21 and N21. If a source voltage is decreased without scaling threshold voltage, the operation margin of each transistor decreases to deteriorate the accuracy of impedance adjustment.
(2) The difference in impedance adjustment between the pull-up side and pull-down side of the prior art of FIG. 2 will be studied.
FIG. 3 shows simplified current paths of the circuit of FIG. 2 represented with dividing resistors. A current path Ia includes a variable resistor R (PMOS transistor P21) and the external resistor RQ connected in series. A current path Ib includes a variable resistor R' (PMOS transistor P23) and the pull-down dummy buffer Ndm connected in series. A current path Ic includes the pull-up dummy buffer Pdm and a variable resistor R" (NMOS transistor N23) connected in series. The variable resistors R, R', and R" are adjusted to equalize potential at each of intermediate connection nodes n1, n2, and n3 with VDDQ/2.
In the current paths Ia and lb, the resistor RQ and the dummy buffer Ndm have each a voltage difference of VDDQ/2. The variable resistors R and R' are connected to the power source VDD, and therefore, have each a voltage difference of (VDD-VDDQ/2). On the other hand, the current path Ic has the dummy buffer Pdm on the power source side, and therefore, the source terminal of the dummy buffer Pdm is at VDDQ that is supplied to the pull-up transistors of the output buffer.
To control the voltage applied to the dummy buffer Pdm to VDDQ/2, the intermediate connection node n3 should be VDDQ/2. As a result, a voltage applied to the variable resistor R" becomes VDDQ/2. Therefore, the larger voltage should be applied to the variable resistor R" since the variable resistor R" is the transistor that must be driven in a saturation region.
VDDQ for driving the output buffer is usually lower than VDD, and therefore, the following is established: EQU (VDD-VDDQ/2)&gt;VDDQ/2
Namely, the voltage applied to the pull-up control variable resistor R" is lower than the voltage applied to the variable resistors R and R'. Even if the pull-down part has a large power source margin, the low power source margin of the pull-up part determines a total power source margin, to deteriorate the performance of the circuit as a whole.
(3) The prior art of FIG. 2 employs VDD to control the potential of the intermediate connection nodes nl to n3 to VDDQ/2. Accordingly, the impedance adjustment accuracy of the circuit of FIG. 2 is affected by noise in VDD as well as noise in VDDQ.